"Hardware Acceleration of Parallel Lagged-Fibonacci Pseudo Random Number ..."

Yu Bi et al. (2006)

> Home

Details and statistics

DOI: —

access: unavailable

type: Conference or Workshop Paper

metadata version: 2007-02-14

- no documents available
- export record
  dblp key:
  - conf/ersa/BiPWH06
- ask others
- share record
  persistent URL:
  - https://dblp.org/rec/conf/ersa/BiPWH06
Yu Bi, Gregory D. Peterson, G. Lee Warren, Robert J. Harrison:
Hardware Acceleration of Parallel Lagged-Fibonacci Pseudo Random Number Generation. ERSA 2006: 215-218

a service of

manage site settings

To protect your privacy, all features that rely on external API calls from your browser are turned off by default. You need to opt-in for them to become active. All settings here will be stored as cookies with your web browser. For more information see our F.A.Q.