"A 6.2mW 7b 3.5GS/s time interleaved 2-stage pipelined ADC in 40nm CMOS."

Annachiara Spagnolo et al. (2014)

> Home

Details and statistics

DOI: 10.1109/ESSCIRC.2014.6942025

access: closed

type: Conference or Workshop Paper

metadata version: 2017-06-02

- view
  - electronic edition via DOI
  - unpaywalled version
  authority control:
- export record
  dblp key:
  - conf/esscirc/SpagnoloVDW14
- ask others
- share record
  persistent URL:
  - https://dblp.org/rec/conf/esscirc/SpagnoloVDW14
Annachiara Spagnolo, Bob Verbruggen, Stefano D'Amico, Piet Wambacq:
A 6.2mW 7b 3.5GS/s time interleaved 2-stage pipelined ADC in 40nm CMOS. ESSCIRC 2014: 75-78

manage site settings

To protect your privacy, all features that rely on external API calls from your browser are turned off by default. You need to opt-in for them to become active. All settings here will be stored as cookies with your web browser. For more information see our F.A.Q.