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"Scaling of Trigate nanowire (NW) MOSFETs Down to 5 nm Width: 300 K ..."

Veeresh Deshpande et al. (2012)

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DOI: 10.1109/ESSDERC.2012.6343348

access: closed

type: Conference or Workshop Paper

metadata version: 2022-11-04

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  dblp key:
  - conf/essderc/DeshpandeBJWVCRVTVTPPPSF12
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  - https://dblp.org/rec/conf/essderc/DeshpandeBJWVCRVTVTPPPSF12
Veeresh Deshpande, Sylvain Barraud, Xavier Jehl, Romain Wacquez, Maud Vinet, Remi Coquand, B. Roche, B. Voisin, François Triozon, C. Vizioz, L. Tosti, Bernard Previtali, P. Perreau, T. Poiroux, Marc Sanquer, Olivier Faynot:
Scaling of Trigate nanowire (NW) MOSFETs Down to 5 nm Width: 300 K transition to Single Electron Transistor, challenges and opportunities. ESSDERC 2012: 121-124

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