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"An architecture for synthesis of testable finite state machines."

Vishwani D. Agrawal, Kwang-Ting Cheng (1990)

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DOI: 10.1109/EDAC.1990.136719

access: closed

type: Conference or Workshop Paper

metadata version: 2017-05-24

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  dblp key:
  - conf/eurodac/AgrawalC90
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  persistent URL:
  - https://dblp.org/rec/conf/eurodac/AgrawalC90
Vishwani D. Agrawal, Kwang-Ting Cheng:
An architecture for synthesis of testable finite state machines. EURO-DAC 1990: 612-616

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