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ORCID"Flexible timing specification in a VHDL synthesis subset."
A. Stoll, Jörg Biesenack, Steffen Rumler (1992)
- A. Stoll, Jörg Biesenack, Steffen Rumler:
Flexible timing specification in a VHDL synthesis subset. EURO-DAC 1992: 610-615
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