"Modeling Bit Multiplication Blocks for DSP Applications Using VHDL."

Siddika Berna Örs, Ahmet Dervisoglu (1999)

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DOI: 10.1109/EURMIC.1999.794500

access: closed

type: Conference or Workshop Paper

metadata version: 2023-03-24

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Siddika Berna Örs, Ahmet Dervisoglu:
Modeling Bit Multiplication Blocks for DSP Applications Using VHDL. EUROMICRO 1999: 1402-1405

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