"A low-power VLSI architecture for face verification using elastic graph ..."

Jean-Luc Nagel et al. (2002)

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DOI: —

access: closed

type: Conference or Workshop Paper

metadata version: 2021-08-09

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  dblp key:
  - conf/eusipco/NagelSAP02
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  persistent URL:
  - https://dblp.org/rec/conf/eusipco/NagelSAP02
Jean-Luc Nagel, Patrick Stadelmann, Michael Ansorge, Fausto Pellandini:
A low-power VLSI architecture for face verification using elastic graph matching. EUSIPCO 2002: 1-4

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