"Error rate estimation of a design implemented in an FPGA based on the ..."

Marc Alexandre Kacou et al. (2017)

> Home

Details and statistics

DOI: 10.1109/EWDTS.2017.8110059

access: closed

type: Conference or Workshop Paper

metadata version: 2023-03-23

- view
  authority control:
- export record
  dblp key:
  - conf/ewdts/KacouGRC17
- ask others
- share record
  persistent URL:
  - https://dblp.org/rec/conf/ewdts/KacouGRC17
Marc Alexandre Kacou, Fakhreddine Ghaffari, Olivier Romain, Bruno Condamin:
Error rate estimation of a design implemented in an FPGA based on the operating conditions. EWDTS 2017: 1-7

manage site settings

To protect your privacy, all features that rely on external API calls from your browser are turned off by default. You need to opt-in for them to become active. All settings here will be stored as cookies with your web browser. For more information see our F.A.Q.