"Low power digital design in FPGAs (poster abstract): a study of pipeline ..."

Andrés D. García, Jean-Luc Danger, Wayne P. Burleson (2000)

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DOI: 10.1145/329166.329220

access: closed

type: Conference or Workshop Paper

metadata version: 2018-11-06

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Andrés D. García, Jean-Luc Danger, Wayne P. Burleson:
Low power digital design in FPGAs (poster abstract): a study of pipeline architectures implemented in a FPGA using a low supply voltage to reduce power consumption. FPGA 2000: 220

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