"An Energy-Efficient Design-Time Scheduler for FPGAs Leveraging Dynamic ..."

Wei Ting Loke, Chin Yang Koay (2017)

> Home

Details and statistics

DOI: —

access: closed

type: Conference or Workshop Paper

metadata version: 2017-02-03

- view
  - electronic edition @ acm.org
- export record
  dblp key:
  - conf/fpga/LokeK17
- ask others
- share record
  persistent URL:
  - https://dblp.org/rec/conf/fpga/LokeK17
Wei Ting Loke, Chin Yang Koay:
An Energy-Efficient Design-Time Scheduler for FPGAs Leveraging Dynamic Frequency Scaling Emulation (Abstract Only). FPGA 2017: 296

a service of

manage site settings

To protect your privacy, all features that rely on external API calls from your browser are turned off by default. You need to opt-in for them to become active. All settings here will be stored as cookies with your web browser. For more information see our F.A.Q.