"Automatic generation of high-performance multipliers for FPGAs with ..."

Shreesha Srinath, Katherine Compton (2010)

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DOI: 10.1145/1723112.1723123

access: closed

type: Conference or Workshop Paper

metadata version: 2018-11-06

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Shreesha Srinath, Katherine Compton:
Automatic generation of high-performance multipliers for FPGAs with asymmetric multiplier blocks. FPGA 2010: 51-58

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