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"Decimal multiplier on FPGA using embedded binary multipliers."

Horácio C. Neto, Mário P. Véstias (2008)

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DOI: 10.1109/FPL.2008.4629931

access: closed

type: Conference or Workshop Paper

metadata version: 2017-06-02

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Horácio C. Neto, Mário P. Véstias:
Decimal multiplier on FPGA using embedded binary multipliers. FPL 2008: 197-202

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