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"Runtime-Programmable Pipelines for Model Checkers on FPGAs."

Mrunal Patel et al. (2019)

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DOI: 10.1109/FPL.2019.00018

access: closed

type: Conference or Workshop Paper

metadata version: 2020-09-05

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  dblp key:
  - conf/fpl/PatelCFM19
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  - https://dblp.org/rec/conf/fpl/PatelCFM19
Mrunal Patel, Shenghsun Cho, Michael Ferdman, Peter A. Milder:
Runtime-Programmable Pipelines for Model Checkers on FPGAs. FPL 2019: 51-58

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