"A technique for minimizing power during FPGA placement."

Kristofer Vorwerk et al. (2008)

> Home

Details and statistics

DOI: 10.1109/FPL.2008.4629937

access: closed

type: Conference or Workshop Paper

metadata version: 2017-05-21

- view
  - electronic edition via DOI
  - unpaywalled version
  authority control:
- export record
  dblp key:
  - conf/fpl/VorwerkRDHKK08
- ask others
- share record
  persistent URL:
  - https://dblp.org/rec/conf/fpl/VorwerkRDHKK08
Kristofer Vorwerk, Madhu Raman, Julien Dunoyer, Yaun-Chung Hsu, Arun Kundu, Andrew A. Kennings:
A technique for minimizing power during FPGA placement. FPL 2008: 233-238

manage site settings

To protect your privacy, all features that rely on external API calls from your browser are turned off by default. You need to opt-in for them to become active. All settings here will be stored as cookies with your web browser. For more information see our F.A.Q.