Stop the war!

Остановите войну!

for scientists:

default search action

combined dblp search
author search
venue search
publication search

ask others

"FPGAs with Reconfigurable Threshold Logic Gates for Improved Performance, ..."

Ankit Wagle et al. (2018)

> Home

Details and statistics

DOI: 10.1109/FPL.2018.00051

access: closed

type: Conference or Workshop Paper

metadata version: 2023-11-12

- view
  authority control:
- export record
  dblp key:
  - conf/fpl/WagleYDV18
- ask others
- share record
  persistent URL:
  - https://dblp.org/rec/conf/fpl/WagleYDV18
Ankit Wagle, Jinghua Yang, Aykut Dengi, Sarma B. K. Vrudhula:
FPGAs with Reconfigurable Threshold Logic Gates for Improved Performance, Power and Area. FPL 2018: 256-259

a service of

manage site settings

To protect your privacy, all features that rely on external API calls from your browser are turned off by default. You need to opt-in for them to become active. All settings here will be stored as cookies with your web browser. For more information see our F.A.Q.