"Reducing parity generation latency through input value aware circuits."

Yusuf Osmanlioglu, Yusuf Onur Koçberber, Oguz Ergin (2009)

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DOI: 10.1145/1531542.1531570

access: closed

type: Conference or Workshop Paper

metadata version: 2021-10-14

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Yusuf Osmanlioglu, Yusuf Onur Koçberber, Oguz Ergin:
Reducing parity generation latency through input value aware circuits. ACM Great Lakes Symposium on VLSI 2009: 109-112

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