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"Timing diagram for CNPC interleaver implementation on FPGA."

Gwonhan Mun, Kunseok Kang, Daeho Kim (2021)

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DOI: 10.1109/ICAIIC51459.2021.9415266

access: closed

type: Conference or Workshop Paper

metadata version: 2024-03-09

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Gwonhan Mun, Kunseok Kang, Daeho Kim:
Timing diagram for CNPC interleaver implementation on FPGA. ICAIIC 2021: 381-384

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