Stop the war!

Остановите войну!

for scientists:

default search action

combined dblp search
author search
venue search
publication search

ask others

"A unified algorithm for gate sizing and clock skew optimization to ..."

Name: dblp XML data dump
Creator: Schloss Dagstuhl - Leibniz Center for Informatics
Published: 1993
License: https://creativecommons.org/publicdomain/zero/1.0/
Keywords: dblp, XML, computer science, scholarly publications, metadata

Weitong Chuang, Sachin S. Sapatnekar, Ibrahim N. Hajj (1993)

> Home

Details and statistics

DOI: 10.1109/ICCAD.1993.580060

access: closed

type: Conference or Workshop Paper

metadata version: 2023-03-24

- view
  authority control:
- export record
  dblp key:
  - conf/iccad/ChuangSH93
- ask others
- share record
  persistent URL:
  - https://dblp.org/rec/conf/iccad/ChuangSH93
Weitong Chuang, Sachin S. Sapatnekar, Ibrahim N. Hajj:
A unified algorithm for gate sizing and clock skew optimization to minimize sequential circuit area. ICCAD 1993: 220-223

a service of

manage site settings

To protect your privacy, all features that rely on external API calls from your browser are turned off by default. You need to opt-in for them to become active. All settings here will be stored as cookies with your web browser. For more information see our F.A.Q.