"A Low Power Miller Compensation Technique for Two Stage Op-amp in 65nm ..."

Rajasekhar Nagulapalli et al. (2019)

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DOI: 10.1109/ICCCNT45670.2019.8944553

access: closed

type: Conference or Workshop Paper

metadata version: 2020-09-05

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Rajasekhar Nagulapalli, Khaled Hayatleh, Steve Barker, B. Naresh Kumar Reddy, B. Seetharamulu:
A Low Power Miller Compensation Technique for Two Stage Op-amp in 65nm CMOS Technology. ICCCNT 2019: 1-5

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