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"Power model analysis using variable rate clock network in CMOS processor."
T. Joby Titus et al. (2016)
- T. Joby Titus, V. Vijayakumari, B. Saranya, V. S. Sanjana Devi:
Power model analysis using variable rate clock network in CMOS processor. ICCCNT 2016: 33:1-33:5
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