Stop the war!

Остановите войну!

for scientists:

default search action

combined dblp search
author search
venue search
publication search

ask others

"Power model analysis using variable rate clock network in CMOS processor."

T. Joby Titus et al. (2016)

> Home

Details and statistics

DOI: 10.1145/2967878.2967915

access: closed

type: Conference or Workshop Paper

metadata version: 2021-10-14

- view
  - electronic edition via DOI
  - unpaywalled version
  authority control:
- export record
  dblp key:
  - conf/icccnt/TitusVSD16
- ask others
- share record
  persistent URL:
  - https://dblp.org/rec/conf/icccnt/TitusVSD16
T. Joby Titus, V. Vijayakumari, B. Saranya, V. S. Sanjana Devi:
Power model analysis using variable rate clock network in CMOS processor. ICCCNT 2016: 33:1-33:5

a service of

manage site settings

To protect your privacy, all features that rely on external API calls from your browser are turned off by default. You need to opt-in for them to become active. All settings here will be stored as cookies with your web browser. For more information see our F.A.Q.