"Repeater insertion combined with LGR methodology for on-chip interconnect ..."

Michael Moreinis et al. (2004)

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DOI: 10.1109/ICECS.2004.1399630

access: closed

type: Conference or Workshop Paper

metadata version: 2017-05-23

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Michael Moreinis, Arkadiy Morgenshtein, Israel A. Wagner, Avinoam Kolodny:
Repeater insertion combined with LGR methodology for on-chip interconnect timing optimization. ICECS 2004: 125-128

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