![](https://dblp.org/img/logo.ua.320x120.png)
![](https://dblp.org/img/dropdown.dark.16x16.png)
![](https://dblp.org/img/peace.dark.16x16.png)
Остановите войну!
for scientists:
![search dblp search dblp](https://dblp.org/img/search.dark.16x16.png)
![search dblp](https://dblp.org/img/search.dark.16x16.png)
default search action
"Modular architecture for a family of multilevel 256/192/128/64 Mbit ..."
Andrea Silvagni et al. (2001)
- Andrea Silvagni, Stefano Zanardi, Alessandro Manstretta, Marco Scotti, Luca Crippa, Giancarlo Ragone, Giuseppe Fusillo, Giovanni Campardo, Osama Khouri, Marcello Stefanelli:
Modular architecture for a family of multilevel 256/192/128/64 Mbit 2-bit/cell 3 V-only NOR flash memory devices. ICECS 2001: 937-940
![](https://dblp.org/img/cog.dark.24x24.png)
manage site settings
To protect your privacy, all features that rely on external API calls from your browser are turned off by default. You need to opt-in for them to become active. All settings here will be stored as cookies with your web browser. For more information see our F.A.Q.