"Modular architecture for a family of multilevel 256/192/128/64 Mbit ..."

Andrea Silvagni et al. (2001)

> Home

Details and statistics

DOI: 10.1109/ICECS.2001.957627

access: closed

type: Conference or Workshop Paper

metadata version: 2021-01-18

- view
  - electronic edition via DOI
  - unpaywalled version
  authority control:
- export record
  dblp key:
  - conf/icecsys/SilvagniZMSCRFC01
- ask others
- share record
  persistent URL:
  - https://dblp.org/rec/conf/icecsys/SilvagniZMSCRFC01
Andrea Silvagni, Stefano Zanardi, Alessandro Manstretta, Marco Scotti, Luca Crippa, Giancarlo Ragone, Giuseppe Fusillo, Giovanni Campardo, Osama Khouri, Marcello Stefanelli:
Modular architecture for a family of multilevel 256/192/128/64 Mbit 2-bit/cell 3 V-only NOR flash memory devices. ICECS 2001: 937-940

manage site settings

To protect your privacy, all features that rely on external API calls from your browser are turned off by default. You need to opt-in for them to become active. All settings here will be stored as cookies with your web browser. For more information see our F.A.Q.