"FPGA Based Hardware Accelerator Design for Convolution Process in ..."

Ardian Dwi C, Trio Adiono, Nana Sutisna (2021)

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DOI: 10.1109/ICEEI52609.2021.9611126

access: closed

type: Conference or Workshop Paper

metadata version: 2021-11-30

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Ardian Dwi C, Trio Adiono, Nana Sutisna:
FPGA Based Hardware Accelerator Design for Convolution Process in Convolutional Neural Network. ICEEI 2021: 1-5

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