"Energy/Performance Design of Memory Hierarchies for Processor-in-Memory Chips."

Michael C. Huang et al. (2000)

> Home

Details and statistics

DOI: 10.1007/3-540-44570-6_11

access: closed

type: Conference or Workshop Paper

metadata version: 2021-12-03

- view
  - electronic edition via DOI
  - unpaywalled version
  authority control:
- export record
  dblp key:
  - conf/ims/HuangRYT00
- ask others
- share record
  persistent URL:
  - https://dblp.org/rec/conf/ims/HuangRYT00
Michael C. Huang, Jose Renau, Seung-Moon Yoo, Josep Torrellas:
Energy/Performance Design of Memory Hierarchies for Processor-in-Memory Chips. Intelligent Memory Systems 2000: 152-159

manage site settings

To protect your privacy, all features that rely on external API calls from your browser are turned off by default. You need to opt-in for them to become active. All settings here will be stored as cookies with your web browser. For more information see our F.A.Q.