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"A 1.25-Gb/s digitally-controlled dual-loop clock and data recovery circuit ..."
Chang-Kyung Seong, Seung-Woo Lee, Woo-Young Choi (2006)
- Chang-Kyung Seong, Seung-Woo Lee, Woo-Young Choi:
A 1.25-Gb/s digitally-controlled dual-loop clock and data recovery circuit with enhanced phase resolution. ISCAS 2006
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