"A 4.5-Track Standard Cell Library with Buried Power Rails in 7nm Node."

Kai-Jie Tong et al. (2025)

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DOI: 10.1109/ISCAS56072.2025.11043668

access: closed

type: Conference or Workshop Paper

metadata version: 2025-07-08

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Kai-Jie Tong, Ting-An Jian, Shang-Mou Zhou, Yi-Jia Wu, Bo-Xiang Yang, Meng-Ru Lin, Ming-Yi Huang, Shi-Xian Tang, Ya-Zhu Yang, Zheng-Jie Peng, Yu-Cheng Lin, Rung-Bin Lin:
A 4.5-Track Standard Cell Library with Buried Power Rails in 7nm Node. ISCAS 2025: 1-5

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