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"VLSI architecture of digital matched filter and prime interleaver for W-CDMA."

Yoshihiro Uchida et al. (2002)

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DOI: 10.1109/ISCAS.2002.1010212

access: closed

type: Conference or Workshop Paper

metadata version: 2017-05-26

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  - conf/iscas/UchidaIOSA02
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  - https://dblp.org/rec/conf/iscas/UchidaIOSA02
Yoshihiro Uchida, Masanao Ise, Takao Onoye, Isao Shirakawa, Itthichai Arungsrisangchai:
VLSI architecture of digital matched filter and prime interleaver for W-CDMA. ISCAS (3) 2002: 269-272

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