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"Fast FPGA-based pipelined digit-serial/parallel multipliers."
Javier Valls et al. (1999)
- Javier Valls, Trini Sansaloni, Marcos Martínez-Peiró, Eduardo I. Boemo:
Fast FPGA-based pipelined digit-serial/parallel multipliers. ISCAS (1) 1999: 482-485
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