"A Digital-Serial VLSI Architecture for Delayed LMS Adaptive FIR Filttering."

Chin-Liang Wang, Ching-Chia Chen, Che-Fu Chen (1995)

> Home

Details and statistics

DOI: 10.1109/ISCAS.1995.521571

access: closed

type: Conference or Workshop Paper

metadata version: 2017-05-26

- view
  - electronic edition via DOI
  - unpaywalled version
  authority control:
- export record
  dblp key:
  - conf/iscas/WangCC95
- ask others
- share record
  persistent URL:
  - https://dblp.org/rec/conf/iscas/WangCC95
Chin-Liang Wang, Ching-Chia Chen, Che-Fu Chen:
A Digital-Serial VLSI Architecture for Delayed LMS Adaptive FIR Filttering. ISCAS 1995: 545-548

manage site settings

To protect your privacy, all features that rely on external API calls from your browser are turned off by default. You need to opt-in for them to become active. All settings here will be stored as cookies with your web browser. For more information see our F.A.Q.