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"A 0.6V 50-to-145MHz PVT tolerant digital PLL with DCO-dedicated ..."

Yudong Zhang et al. (2017)

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DOI: 10.1109/ISCAS.2017.8050743

access: closed

type: Conference or Workshop Paper

metadata version: 2023-08-11

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Yudong Zhang, Xiaofeng Liu, Woogeun Rhee, Hanjun Jiang, Zhihua Wang:
A 0.6V 50-to-145MHz PVT tolerant digital PLL with DCO-dedicated ΔΣ LDO and temperature compensation circuits in 65nm CMOS. ISCAS 2017: 1-4

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