"Consequence of Various Clock Parameters on Power / Timing Analysis for ..."

Subhadeep Nag et al. (2024)

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DOI: 10.1109/ISES63344.2024.00085

access: closed

type: Conference or Workshop Paper

metadata version: 2025-07-04

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Subhadeep Nag, Suman Kalyan Porel, Dyuti Sengupta, Aniruddha Chandra, Hemanta Kumar Mondal:
Consequence of Various Clock Parameters on Power / Timing Analysis for VLSI Circuits. iSES 2024: 376-379

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