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"Transistor-level monolithic 3D standard cell layout optimization for ..."

Bon Woong Ku et al. (2017)

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DOI: 10.1109/ISLPED.2017.8009189

access: closed

type: Conference or Workshop Paper

metadata version: 2022-10-02

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  dblp key:
  - conf/islped/KuSNL17
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Bon Woong Ku, Taigon Song, Arthur Nieuwoudt, Sung Kyu Lim:
Transistor-level monolithic 3D standard cell layout optimization for full-chip static power integrity. ISLPED 2017: 1-6

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