"Generation of SystemVerilog Observers from SysML and MARTE/CCSL."

Aamir M. Khan, Muhammad Rashid (2016)

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DOI: 10.1109/ISORC.2016.18

access: closed

type: Conference or Workshop Paper

metadata version: 2023-03-24

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Aamir M. Khan, Muhammad Rashid:
Generation of SystemVerilog Observers from SysML and MARTE/CCSL. ISORC 2016: 61-68

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