"Chip-Level Substrate Noise Analysis with Network Reduction by Fundamental ..."

Yoshitaka Murasaka et al. (2001)

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DOI: 10.1109/ISQED.2001.915275

access: closed

type: Conference or Workshop Paper

metadata version: 2023-03-23

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Yoshitaka Murasaka, Makoto Nagata, Takafumi Ohmoto, Takashi Morie, Atsushi Iwata:
Chip-Level Substrate Noise Analysis with Network Reduction by Fundamental Matrix Computation. ISQED 2001: 482-487

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