"29.5 A 3nm 3.6GHz Dual-Port SRAM with Backend-RC Optimization and a ..."

Hidehiro Fujiwara et al. (2025)

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DOI: 10.1109/ISSCC49661.2025.10904736

access: closed

type: Conference or Workshop Paper

metadata version: 2025-04-25

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Hidehiro Fujiwara, Wei-Chang Zhao, Kinshuk Khare, Yi-Hsin Nien, Chih-Yu Lin, Cheng-Han Lin, Shan-Ru Liao, Kenta Torigoe, Shirleen Xia, Yuichiro Ishii, Yao-Yi Lin, Jhon-Jhy Liaw, Yen-Huei Chen, Hung-Jen Liao, Tsung-Yung Jonathan Chang:
29.5 A 3nm 3.6GHz Dual-Port SRAM with Backend-RC Optimization and a Far-End Write-Assist Scheme. ISSCC 2025: 500-502

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