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"13.10 A 4nm 48Gb/s/wire Single-Ended NRZ Parallel Transceiver with ..."

Kihwan Seong et al. (2024)

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DOI: 10.1109/ISSCC49657.2024.10454481

access: closed

type: Conference or Workshop Paper

metadata version: 2024-03-19

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  dblp key:
  - conf/isscc/SeongOLBSLKKKMLKLPYRS24
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Kihwan Seong, Wooseuk Oh, Hyunwoo Lee, Gyeom-Je Bae, Youngseob Suh, Hyemun Lee, Juyoung Kim, Eunsu Kim, Yeongeon Kang, Gunhu Mo, Youjin Lee, Mingyeong Kim, Seongno Lee, Donguk Park, Byoung-Joo Yoo, Hyo-Gyuem Rhew, Jongshin Shin:
13.10 A 4nm 48Gb/s/wire Single-Ended NRZ Parallel Transceiver with Offset-Calibration and Equalization Schemes for Next-Generation Memory Interfaces and Chiplets. ISSCC 2024: 250-252

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