Stop the war!

Остановите войну!

for scientists:

default search action

combined dblp search
author search
venue search
publication search

ask others

"A 2 ×30k-Spin Multichip Scalable Annealing Processor Based on a ..."

Takashi Takemoto et al. (2019)

> Home

Details and statistics

DOI: 10.1109/ISSCC.2019.8662517

access: closed

type: Conference or Workshop Paper

metadata version: 2019-03-12

- view
  - electronic edition via DOI
  - unpaywalled version
  authority control:
- export record
  dblp key:
  - conf/isscc/TakemotoHYY19
- ask others
- share record
  persistent URL:
  - https://dblp.org/rec/conf/isscc/TakemotoHYY19
Takashi Takemoto, Masato Hayashi, Chihiro Yoshimura, Masanao Yamaoka:
A 2 ×30k-Spin Multichip Scalable Annealing Processor Based on a Processing-In-Memory Approach for Solving Large-Scale Combinatorial Optimization Problems. ISSCC 2019: 52-54

a service of

manage site settings

To protect your privacy, all features that rely on external API calls from your browser are turned off by default. You need to opt-in for them to become active. All settings here will be stored as cookies with your web browser. For more information see our F.A.Q.