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"2.3 A 220GOPS 96-Core Processor with 6 Chiplets 3D-Stacked on an Active ..."

Pascal Vivet et al. (2020)

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DOI: 10.1109/ISSCC19947.2020.9062927

access: closed

type: Conference or Workshop Paper

metadata version: 2024-05-07

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  - conf/isscc/VivetGTPMMTDBVP20
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  - https://dblp.org/rec/conf/isscc/VivetGTPMMTDBVP20
Pascal Vivet, Eric Guthmuller, Yvain Thonnart, Gaël Pillonnet, Guillaume Moritz, Ivan Miro-Panades, César Fuguet Tortolero, Jean Durupt, Christian Bernard, Didier Varreau, Julian J. H. Pontes, Sébastien Thuries, David Coriat, Michel Harrand, Denis Dutoit, Didier Lattard, Lucile Arnaud, Jean Charbonnier, Perceval Coudrain, Arnaud Garnier, Frédéric Berger, Alain Gueugnot, Alain Greiner, Quentin L. Meunier, Alexis Farcy, Alexandre Arriordaz, Séverine Cheramy, Fabien Clermidy:
2.3 A 220GOPS 96-Core Processor with 6 Chiplets 3D-Stacked on an Active Interposer Offering 0.6ns/mm Latency, 3Tb/s/mm² Inter-Chiplet Interconnects and 156mW/mm²@ 82%-Peak-Efficiency DC-DC Converters. ISSCC 2020: 46-48

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