"CMOS IC Design and Verilog-A Modelling of 10-Gb/s PLL-Based Deserializer ..."

Maher Assaad, David R. S. Cumming (2007)

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DOI: 10.1109/ISSOC.2007.4427420

access: closed

type: Conference or Workshop Paper

metadata version: 2024-02-05

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Maher Assaad, David R. S. Cumming:
CMOS IC Design and Verilog-A Modelling of 10-Gb/s PLL-Based Deserializer for Inter-Chip Communication in SOC. SoC 2007: 1-4

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