"Timing Macro Modeling for Efficient Hierarchical Timing Analysis."

Iris Hui-Ru Jiang, Pei-Yu Lee (2018)

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DOI: 10.1109/ISVLSI.2018.00134

access: closed

type: Conference or Workshop Paper

metadata version: 2023-03-24

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Iris Hui-Ru Jiang, Pei-Yu Lee:
Timing Macro Modeling for Efficient Hierarchical Timing Analysis. ISVLSI 2018: 714

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