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"Design of Low Power 4-Bit 400MS/s Standard Cell Based Flash ADC."

S. M. Mayur et al. (2017)

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DOI: 10.1109/ISVLSI.2017.111

access: closed

type: Conference or Workshop Paper

metadata version: 2023-03-24

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  dblp key:
  - conf/isvlsi/MayurSNV17
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  persistent URL:
  - https://dblp.org/rec/conf/isvlsi/MayurSNV17
S. M. Mayur, Siddharth R. K., Kumar Y. B. Nithin, M. H. Vasantha:
Design of Low Power 4-Bit 400MS/s Standard Cell Based Flash ADC. ISVLSI 2017: 600-603

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