"ASIC Design Flow Using Simulink and Cadence Digital IC Design Tools."

Charanya K. Rao, Ashmitha Talluri, Ava Hedayatipour (2025)

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DOI: 10.1109/ISVLSI65124.2025.11130260

access: closed

type: Conference or Workshop Paper

metadata version: 2025-09-02

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Charanya K. Rao, Ashmitha Talluri, Ava Hedayatipour:
ASIC Design Flow Using Simulink and Cadence Digital IC Design Tools. ISVLSI 2025: 1-5

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