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"Design of Low Power SAR ADC Using Clock Retiming."

Name: dblp XML data dump
Creator: Schloss Dagstuhl - Leibniz Center for Informatics
Published: 1993
License: https://creativecommons.org/publicdomain/zero/1.0/
Keywords: dblp, XML, computer science, scholarly publications, metadata

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Jalaja S, Vijaya Prakash A. M (2018)

Dagstuhl

Trier

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DOI: 10.1109/ISVLSI.2018.00042

access: closed

type: Conference or Workshop Paper

metadata version: 2023-03-24

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Jalaja S, Vijaya Prakash A. M:
Design of Low Power SAR ADC Using Clock Retiming. ISVLSI 2018: 181-186

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last updated on 2023-03-24 00:02 CET by the dblp team

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