"Test Methodology for Motorola's High Performance e500 Core Based on ..."

Robert Bailey et al. (2002)

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DOI: 10.1109/TEST.2002.1041808

access: closed

type: Conference or Workshop Paper

metadata version: 2023-03-23

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Robert Bailey, A. Metayer, B. Svrcek, Nandu Tendolkar, E. Wolf, Eric Fiene, Mike Alexander, Rick Woltenberg, Rajesh Raina:
Test Methodology for Motorola's High Performance e500 Core Based on PowerPC Instruction Set Architecture. ITC 2002: 574-583

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