


default search action
"Using a hierarchical DfT methodology in high frequency processor designs ..."
Michael Kessler et al. (2001)
- Michael Kessler, Gundolf Kiefer, Jens Leenstra, Knut Schünemann, Thomas Schwarz, Hans-Joachim Wunderlich:

Using a hierarchical DfT methodology in high frequency processor designs for improved delay fault testability. ITC 2001: 461-469

manage site settings
To protect your privacy, all features that rely on external API calls from your browser are turned off by default. You need to opt-in for them to become active. All settings here will be stored as cookies with your web browser. For more information see our F.A.Q.


Google
Google Scholar
Semantic Scholar
Internet Archive Scholar
CiteSeerX
ORCID













