Stop the war!

Остановите войну!

for scientists:

default search action

combined dblp search
author search
venue search
publication search

ask others

"Transistor-Level Fault Analysis and Test Algorithm Development for Ternary ..."

Derek Wright, Manoj Sachdev (2003)

> Home

Details and statistics

DOI: 10.1109/TEST.2003.1270823

access: closed

type: Conference or Workshop Paper

metadata version: 2023-03-23

- view
  authority control:
- export record
  dblp key:
  - conf/itc/WrightS03
- ask others
- share record
  persistent URL:
  - https://dblp.org/rec/conf/itc/WrightS03
Derek Wright, Manoj Sachdev:
Transistor-Level Fault Analysis and Test Algorithm Development for Ternary Dynamic Content Addressable Memorie. ITC 2003: 39-47

a service of

manage site settings

To protect your privacy, all features that rely on external API calls from your browser are turned off by default. You need to opt-in for them to become active. All settings here will be stored as cookies with your web browser. For more information see our F.A.Q.