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ORCID"A Code Partitioning Tool for Simulink Models to Implement on FPGA-Based ..."
Satoru Miyasono, Yosuke Moriai, Hiroshi Saito (2014)
- Satoru Miyasono, Yosuke Moriai, Hiroshi Saito:
A Code Partitioning Tool for Simulink Models to Implement on FPGA-Based Network-on-Chip Architecture. MCSoC 2014: 141-148
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