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"Design of UART controller for FPGA with Simulink®."

Name: dblp XML data dump
Creator: Schloss Dagstuhl - Leibniz Center for Informatics
Published: 1993
License: https://creativecommons.org/publicdomain/zero/1.0/
Keywords: dblp, XML, computer science, scholarly publications, metadata

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Jordan Kralev (2014)

Dagstuhl

Trier

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DOI: 10.1109/MECO.2014.6862655

access: closed

type: Conference or Workshop Paper

metadata version: 2021-02-08

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Jordan Kralev:
Design of UART controller for FPGA with Simulink®. MECO 2014: 44-47

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last updated on 2021-02-08 13:26 CET by the dblp team

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