"RRS cache: a low voltage cache based on timing speculation SRAM with a ..."

Xiaojing Shang et al. (2019)

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DOI: 10.1145/3357526.3357535

access: closed

type: Conference or Workshop Paper

metadata version: 2020-01-09

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Xiaojing Shang, Ming Ling, Shan Shen, Tianxiang Shao, Jun Yang:
RRS cache: a low voltage cache based on timing speculation SRAM with a reuse-aware cacheline remapping mechanism. MEMSYS 2019: 451-458

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